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    <h1>File: /Users/paulross/dev/linux/linux-3.13/arch/x86/include/uapi/asm/processor-flags.h</h1>
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    <pre><a name="1" /><span class="Maybe">       1:</span> <span class="f">#</span><span class="n">ifndef</span> <a href="cpu.c_macros_ref.html#_X1VBUElfQVNNX1g4Nl9QUk9DRVNTT1JfRkxBR1NfSF8w"><span class="b">_UAPI_ASM_X86_PROCESSOR_FLAGS_H</span></a>
<a name="2" /><span class="Maybe">       2:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_X1VBUElfQVNNX1g4Nl9QUk9DRVNTT1JfRkxBR1NfSF8w"><span class="b">_UAPI_ASM_X86_PROCESSOR_FLAGS_H</span></a>
<a name="3" /><span class="Maybe">       3:</span> <span class="k">/* Various flags defined: can be included from assembler. */</span>
<a name="4" /><span class="Maybe">       4:</span> 
<a name="5" /><span class="Maybe">       5:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="b">linux</span><span class="f">/</span><span class="m">const</span><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="6" /><span class="Maybe">       6:</span> 
<a name="7" /><span class="Maybe">       7:</span> <span class="k">/*</span>
<a name="8" /><span class="Maybe">       8:</span> <span class="k"> * EFLAGS bits</span>
<a name="9" /><span class="Maybe">       9:</span> <span class="k"> */</span>
<a name="10" /><span class="Maybe">      10:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19DRl9CSVRfMA__"><span class="b">X86_EFLAGS_CF_BIT</span></a>    <span class="c">0</span> <span class="k">/* Carry Flag */</span>
<a name="11" /><span class="Maybe">      11:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19DRl8w"><span class="b">X86_EFLAGS_CF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19DRl9CSVRfMA__"><span class="b">X86_EFLAGS_CF_BIT</span></a><span class="f">)</span>
<a name="12" /><span class="Maybe">      12:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19GSVhFRF9CSVRfMA__"><span class="b">X86_EFLAGS_FIXED_BIT</span></a>    <span class="c">1</span> <span class="k">/* Bit 1 - always on */</span>
<a name="13" /><span class="Maybe">      13:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19GSVhFRF8w"><span class="b">X86_EFLAGS_FIXED</span></a>    <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19GSVhFRF9CSVRfMA__"><span class="b">X86_EFLAGS_FIXED_BIT</span></a><span class="f">)</span>
<a name="14" /><span class="Maybe">      14:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19QRl9CSVRfMA__"><span class="b">X86_EFLAGS_PF_BIT</span></a>    <span class="c">2</span> <span class="k">/* Parity Flag */</span>
<a name="15" /><span class="Maybe">      15:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19QRl8w"><span class="b">X86_EFLAGS_PF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19QRl9CSVRfMA__"><span class="b">X86_EFLAGS_PF_BIT</span></a><span class="f">)</span>
<a name="16" /><span class="Maybe">      16:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BRl9CSVRfMA__"><span class="b">X86_EFLAGS_AF_BIT</span></a>    <span class="c">4</span> <span class="k">/* Auxiliary carry Flag */</span>
<a name="17" /><span class="Maybe">      17:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BRl8w"><span class="b">X86_EFLAGS_AF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BRl9CSVRfMA__"><span class="b">X86_EFLAGS_AF_BIT</span></a><span class="f">)</span>
<a name="18" /><span class="Maybe">      18:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19aRl9CSVRfMA__"><span class="b">X86_EFLAGS_ZF_BIT</span></a>    <span class="c">6</span> <span class="k">/* Zero Flag */</span>
<a name="19" /><span class="Maybe">      19:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19aRl8w"><span class="b">X86_EFLAGS_ZF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19aRl9CSVRfMA__"><span class="b">X86_EFLAGS_ZF_BIT</span></a><span class="f">)</span>
<a name="20" /><span class="Maybe">      20:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19TRl9CSVRfMA__"><span class="b">X86_EFLAGS_SF_BIT</span></a>    <span class="c">7</span> <span class="k">/* Sign Flag */</span>
<a name="21" /><span class="Maybe">      21:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19TRl8w"><span class="b">X86_EFLAGS_SF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19TRl9CSVRfMA__"><span class="b">X86_EFLAGS_SF_BIT</span></a><span class="f">)</span>
<a name="22" /><span class="Maybe">      22:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19URl9CSVRfMA__"><span class="b">X86_EFLAGS_TF_BIT</span></a>    <span class="c">8</span> <span class="k">/* Trap Flag */</span>
<a name="23" /><span class="Maybe">      23:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19URl8w"><span class="b">X86_EFLAGS_TF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19URl9CSVRfMA__"><span class="b">X86_EFLAGS_TF_BIT</span></a><span class="f">)</span>
<a name="24" /><span class="Maybe">      24:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0VGTEFHU19JRl9CSVRfMA__"><span class="b">X86_EFLAGS_IF_BIT</span></a>    <span class="c">9</span> <span class="k">/* Interrupt Flag */</span>
<a name="25" /><span class="Maybe">      25:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0VGTEFHU19JRl8w"><span class="b">X86_EFLAGS_IF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0VGTEFHU19JRl9CSVRfMA__"><span class="b">X86_EFLAGS_IF_BIT</span></a><span class="f">)</span>
<a name="26" /><span class="Maybe">      26:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19ERl9CSVRfMA__"><span class="b">X86_EFLAGS_DF_BIT</span></a>    <span class="c">10</span> <span class="k">/* Direction Flag */</span>
<a name="27" /><span class="Maybe">      27:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19ERl8w"><span class="b">X86_EFLAGS_DF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19ERl9CSVRfMA__"><span class="b">X86_EFLAGS_DF_BIT</span></a><span class="f">)</span>
<a name="28" /><span class="Maybe">      28:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19PRl9CSVRfMA__"><span class="b">X86_EFLAGS_OF_BIT</span></a>    <span class="c">11</span> <span class="k">/* Overflow Flag */</span>
<a name="29" /><span class="Maybe">      29:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19PRl8w"><span class="b">X86_EFLAGS_OF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19PRl9CSVRfMA__"><span class="b">X86_EFLAGS_OF_BIT</span></a><span class="f">)</span>
<a name="30" /><span class="Maybe">      30:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19JT1BMX0JJVF8w"><span class="b">X86_EFLAGS_IOPL_BIT</span></a>    <span class="c">12</span> <span class="k">/* I/O Privilege Level (2 bits) */</span>
<a name="31" /><span class="Maybe">      31:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19JT1BMXzA_"><span class="b">X86_EFLAGS_IOPL</span></a>        <span class="f">(</span><a href="cpu.c_macros_ref.html#_X0FDXzA_"><span class="b">_AC</span></a><span class="f">(</span><span class="c">3</span><span class="f">,</span><span class="b">UL</span><span class="f">)</span> <span class="f">&lt;&lt;</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19JT1BMX0JJVF8w"><span class="b">X86_EFLAGS_IOPL_BIT</span></a><span class="f">)</span>
<a name="32" /><span class="Maybe">      32:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19OVF9CSVRfMA__"><span class="b">X86_EFLAGS_NT_BIT</span></a>    <span class="c">14</span> <span class="k">/* Nested Task */</span>
<a name="33" /><span class="Maybe">      33:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19OVF8w"><span class="b">X86_EFLAGS_NT</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19OVF9CSVRfMA__"><span class="b">X86_EFLAGS_NT_BIT</span></a><span class="f">)</span>
<a name="34" /><span class="Maybe">      34:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19SRl9CSVRfMA__"><span class="b">X86_EFLAGS_RF_BIT</span></a>    <span class="c">16</span> <span class="k">/* Resume Flag */</span>
<a name="35" /><span class="Maybe">      35:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19SRl8w"><span class="b">X86_EFLAGS_RF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19SRl9CSVRfMA__"><span class="b">X86_EFLAGS_RF_BIT</span></a><span class="f">)</span>
<a name="36" /><span class="Maybe">      36:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WTV9CSVRfMA__"><span class="b">X86_EFLAGS_VM_BIT</span></a>    <span class="c">17</span> <span class="k">/* Virtual Mode */</span>
<a name="37" /><span class="Maybe">      37:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WTV8w"><span class="b">X86_EFLAGS_VM</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WTV9CSVRfMA__"><span class="b">X86_EFLAGS_VM_BIT</span></a><span class="f">)</span>
<a name="38" /><span class="Maybe">      38:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BQ19CSVRfMA__"><span class="b">X86_EFLAGS_AC_BIT</span></a>    <span class="c">18</span> <span class="k">/* Alignment Check/Access Control */</span>
<a name="39" /><span class="Maybe">      39:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BQ18w"><span class="b">X86_EFLAGS_AC</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BQ19CSVRfMA__"><span class="b">X86_EFLAGS_AC_BIT</span></a><span class="f">)</span>
<a name="40" /><span class="Maybe">      40:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BQ19CSVRfMA__"><span class="b">X86_EFLAGS_AC_BIT</span></a>    <span class="c">18</span> <span class="k">/* Alignment Check/Access Control */</span>
<a name="41" /><span class="Maybe">      41:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BQ18w"><span class="b">X86_EFLAGS_AC</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19BQ19CSVRfMA__"><span class="b">X86_EFLAGS_AC_BIT</span></a><span class="f">)</span>
<a name="42" /><span class="Maybe">      42:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WSUZfQklUXzA_"><span class="b">X86_EFLAGS_VIF_BIT</span></a>    <span class="c">19</span> <span class="k">/* Virtual Interrupt Flag */</span>
<a name="43" /><span class="Maybe">      43:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WSUZfMA__"><span class="b">X86_EFLAGS_VIF</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WSUZfQklUXzA_"><span class="b">X86_EFLAGS_VIF_BIT</span></a><span class="f">)</span>
<a name="44" /><span class="Maybe">      44:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WSVBfQklUXzA_"><span class="b">X86_EFLAGS_VIP_BIT</span></a>    <span class="c">20</span> <span class="k">/* Virtual Interrupt Pending */</span>
<a name="45" /><span class="Maybe">      45:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WSVBfMA__"><span class="b">X86_EFLAGS_VIP</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19WSVBfQklUXzA_"><span class="b">X86_EFLAGS_VIP_BIT</span></a><span class="f">)</span>
<a name="46" /><span class="Maybe">      46:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19JRF9CSVRfMA__"><span class="b">X86_EFLAGS_ID_BIT</span></a>    <span class="c">21</span> <span class="k">/* CPUID detection */</span>
<a name="47" /><span class="Maybe">      47:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19JRF8w"><span class="b">X86_EFLAGS_ID</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0VGTEFHU19JRF9CSVRfMA__"><span class="b">X86_EFLAGS_ID_BIT</span></a><span class="f">)</span>
<a name="48" /><span class="Maybe">      48:</span> 
<a name="49" /><span class="Maybe">      49:</span> <span class="k">/*</span>
<a name="50" /><span class="Maybe">      50:</span> <span class="k"> * Basic CPU control in CR0</span>
<a name="51" /><span class="Maybe">      51:</span> <span class="k"> */</span>
<a name="52" /><span class="Maybe">      52:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9QRV9CSVRfMA__"><span class="b">X86_CR0_PE_BIT</span></a>        <span class="c">0</span> <span class="k">/* Protection Enable */</span>
<a name="53" /><span class="Maybe">      53:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9QRV8w"><span class="b">X86_CR0_PE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9QRV9CSVRfMA__"><span class="b">X86_CR0_PE_BIT</span></a><span class="f">)</span>
<a name="54" /><span class="Maybe">      54:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9NUF9CSVRfMA__"><span class="b">X86_CR0_MP_BIT</span></a>        <span class="c">1</span> <span class="k">/* Monitor Coprocessor */</span>
<a name="55" /><span class="Maybe">      55:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9NUF8w"><span class="b">X86_CR0_MP</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9NUF9CSVRfMA__"><span class="b">X86_CR0_MP_BIT</span></a><span class="f">)</span>
<a name="56" /><span class="Maybe">      56:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9FTV9CSVRfMA__"><span class="b">X86_CR0_EM_BIT</span></a>        <span class="c">2</span> <span class="k">/* Emulation */</span>
<a name="57" /><span class="Maybe">      57:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9FTV8w"><span class="b">X86_CR0_EM</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9FTV9CSVRfMA__"><span class="b">X86_CR0_EM_BIT</span></a><span class="f">)</span>
<a name="58" /><span class="Maybe">      58:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9UU19CSVRfMA__"><span class="b">X86_CR0_TS_BIT</span></a>        <span class="c">3</span> <span class="k">/* Task Switched */</span>
<a name="59" /><span class="Maybe">      59:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9UU18w"><span class="b">X86_CR0_TS</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9UU19CSVRfMA__"><span class="b">X86_CR0_TS_BIT</span></a><span class="f">)</span>
<a name="60" /><span class="Maybe">      60:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9FVF9CSVRfMA__"><span class="b">X86_CR0_ET_BIT</span></a>        <span class="c">4</span> <span class="k">/* Extension Type */</span>
<a name="61" /><span class="Maybe">      61:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9FVF8w"><span class="b">X86_CR0_ET</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9FVF9CSVRfMA__"><span class="b">X86_CR0_ET_BIT</span></a><span class="f">)</span>
<a name="62" /><span class="Maybe">      62:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9ORV9CSVRfMA__"><span class="b">X86_CR0_NE_BIT</span></a>        <span class="c">5</span> <span class="k">/* Numeric Error */</span>
<a name="63" /><span class="Maybe">      63:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9ORV8w"><span class="b">X86_CR0_NE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9ORV9CSVRfMA__"><span class="b">X86_CR0_NE_BIT</span></a><span class="f">)</span>
<a name="64" /><span class="Maybe">      64:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9XUF9CSVRfMA__"><span class="b">X86_CR0_WP_BIT</span></a>        <span class="c">16</span> <span class="k">/* Write Protect */</span>
<a name="65" /><span class="Maybe">      65:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9XUF8w"><span class="b">X86_CR0_WP</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9XUF9CSVRfMA__"><span class="b">X86_CR0_WP_BIT</span></a><span class="f">)</span>
<a name="66" /><span class="Maybe">      66:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9BTV9CSVRfMA__"><span class="b">X86_CR0_AM_BIT</span></a>        <span class="c">18</span> <span class="k">/* Alignment Mask */</span>
<a name="67" /><span class="Maybe">      67:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9BTV8w"><span class="b">X86_CR0_AM</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9BTV9CSVRfMA__"><span class="b">X86_CR0_AM_BIT</span></a><span class="f">)</span>
<a name="68" /><span class="Maybe">      68:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9OV19CSVRfMA__"><span class="b">X86_CR0_NW_BIT</span></a>        <span class="c">29</span> <span class="k">/* Not Write-through */</span>
<a name="69" /><span class="Maybe">      69:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9OV18w"><span class="b">X86_CR0_NW</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9OV19CSVRfMA__"><span class="b">X86_CR0_NW_BIT</span></a><span class="f">)</span>
<a name="70" /><span class="Maybe">      70:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9DRF9CSVRfMA__"><span class="b">X86_CR0_CD_BIT</span></a>        <span class="c">30</span> <span class="k">/* Cache Disable */</span>
<a name="71" /><span class="Maybe">      71:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9DRF8w"><span class="b">X86_CR0_CD</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9DRF9CSVRfMA__"><span class="b">X86_CR0_CD_BIT</span></a><span class="f">)</span>
<a name="72" /><span class="Maybe">      72:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9QR19CSVRfMA__"><span class="b">X86_CR0_PG_BIT</span></a>        <span class="c">31</span> <span class="k">/* Paging */</span>
<a name="73" /><span class="Maybe">      73:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSMF9QR18w"><span class="b">X86_CR0_PG</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSMF9QR19CSVRfMA__"><span class="b">X86_CR0_PG_BIT</span></a><span class="f">)</span>
<a name="74" /><span class="Maybe">      74:</span> 
<a name="75" /><span class="Maybe">      75:</span> <span class="k">/*</span>
<a name="76" /><span class="Maybe">      76:</span> <span class="k"> * Paging options in CR3</span>
<a name="77" /><span class="Maybe">      77:</span> <span class="k"> */</span>
<a name="78" /><span class="Maybe">      78:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSM19QV1RfQklUXzA_"><span class="b">X86_CR3_PWT_BIT</span></a>        <span class="c">3</span> <span class="k">/* Page Write Through */</span>
<a name="79" /><span class="Maybe">      79:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSM19QV1RfMA__"><span class="b">X86_CR3_PWT</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSM19QV1RfQklUXzA_"><span class="b">X86_CR3_PWT_BIT</span></a><span class="f">)</span>
<a name="80" /><span class="Maybe">      80:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSM19QQ0RfQklUXzA_"><span class="b">X86_CR3_PCD_BIT</span></a>        <span class="c">4</span> <span class="k">/* Page Cache Disable */</span>
<a name="81" /><span class="Maybe">      81:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSM19QQ0RfMA__"><span class="b">X86_CR3_PCD</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSM19QQ0RfQklUXzA_"><span class="b">X86_CR3_PCD_BIT</span></a><span class="f">)</span>
<a name="82" /><span class="Maybe">      82:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSM19QQ0lEX01BU0tfMA__"><span class="b">X86_CR3_PCID_MASK</span></a>    <a href="cpu.c_macros_ref.html#_X0FDXzA_"><span class="b">_AC</span></a><span class="f">(</span><span class="c">0x00000fff</span><span class="f">,</span><span class="b">UL</span><span class="f">)</span> <span class="k">/* PCID Mask */</span>
<a name="83" /><span class="Maybe">      83:</span> 
<a name="84" /><span class="Maybe">      84:</span> <span class="k">/*</span>
<a name="85" /><span class="Maybe">      85:</span> <span class="k"> * Intel CPU features in CR4</span>
<a name="86" /><span class="Maybe">      86:</span> <span class="k"> */</span>
<a name="87" /><span class="Maybe">      87:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9WTUVfQklUXzA_"><span class="b">X86_CR4_VME_BIT</span></a>        <span class="c">0</span> <span class="k">/* enable vm86 extensions */</span>
<a name="88" /><span class="Maybe">      88:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9WTUVfMA__"><span class="b">X86_CR4_VME</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9WTUVfQklUXzA_"><span class="b">X86_CR4_VME_BIT</span></a><span class="f">)</span>
<a name="89" /><span class="Maybe">      89:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QVklfQklUXzA_"><span class="b">X86_CR4_PVI_BIT</span></a>        <span class="c">1</span> <span class="k">/* virtual interrupts flag enable */</span>
<a name="90" /><span class="Maybe">      90:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QVklfMA__"><span class="b">X86_CR4_PVI</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QVklfQklUXzA_"><span class="b">X86_CR4_PVI_BIT</span></a><span class="f">)</span>
<a name="91" /><span class="Maybe">      91:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9UU0RfQklUXzA_"><span class="b">X86_CR4_TSD_BIT</span></a>        <span class="c">2</span> <span class="k">/* disable time stamp at ipl 3 */</span>
<a name="92" /><span class="Maybe">      92:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9UU0RfMA__"><span class="b">X86_CR4_TSD</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9UU0RfQklUXzA_"><span class="b">X86_CR4_TSD_BIT</span></a><span class="f">)</span>
<a name="93" /><span class="Maybe">      93:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9ERV9CSVRfMA__"><span class="b">X86_CR4_DE_BIT</span></a>        <span class="c">3</span> <span class="k">/* enable debugging extensions */</span>
<a name="94" /><span class="Maybe">      94:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9ERV8w"><span class="b">X86_CR4_DE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9ERV9CSVRfMA__"><span class="b">X86_CR4_DE_BIT</span></a><span class="f">)</span>
<a name="95" /><span class="Maybe">      95:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QU0VfQklUXzA_"><span class="b">X86_CR4_PSE_BIT</span></a>        <span class="c">4</span> <span class="k">/* enable page size extensions */</span>
<a name="96" /><span class="Maybe">      96:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QU0VfMA__"><span class="b">X86_CR4_PSE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QU0VfQklUXzA_"><span class="b">X86_CR4_PSE_BIT</span></a><span class="f">)</span>
<a name="97" /><span class="Maybe">      97:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQUVfQklUXzA_"><span class="b">X86_CR4_PAE_BIT</span></a>        <span class="c">5</span> <span class="k">/* enable physical address extensions */</span>
<a name="98" /><span class="Maybe">      98:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQUVfMA__"><span class="b">X86_CR4_PAE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQUVfQklUXzA_"><span class="b">X86_CR4_PAE_BIT</span></a><span class="f">)</span>
<a name="99" /><span class="Maybe">      99:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9NQ0VfQklUXzA_"><span class="b">X86_CR4_MCE_BIT</span></a>        <span class="c">6</span> <span class="k">/* Machine check enable */</span>
<a name="100" /><span class="Maybe">     100:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9NQ0VfMA__"><span class="b">X86_CR4_MCE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9NQ0VfQklUXzA_"><span class="b">X86_CR4_MCE_BIT</span></a><span class="f">)</span>
<a name="101" /><span class="Maybe">     101:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QR0VfQklUXzA_"><span class="b">X86_CR4_PGE_BIT</span></a>        <span class="c">7</span> <span class="k">/* enable global pages */</span>
<a name="102" /><span class="Maybe">     102:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QR0VfMA__"><span class="b">X86_CR4_PGE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QR0VfQklUXzA_"><span class="b">X86_CR4_PGE_BIT</span></a><span class="f">)</span>
<a name="103" /><span class="Maybe">     103:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQ0VfQklUXzA_"><span class="b">X86_CR4_PCE_BIT</span></a>        <span class="c">8</span> <span class="k">/* enable performance counters at ipl 3 */</span>
<a name="104" /><span class="Maybe">     104:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQ0VfMA__"><span class="b">X86_CR4_PCE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQ0VfQklUXzA_"><span class="b">X86_CR4_PCE_BIT</span></a><span class="f">)</span>
<a name="105" /><span class="Maybe">     105:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU0ZYU1JfQklUXzA_"><span class="b">X86_CR4_OSFXSR_BIT</span></a>    <span class="c">9</span> <span class="k">/* enable fast FPU save and restore */</span>
<a name="106" /><span class="Maybe">     106:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU0ZYU1JfMA__"><span class="b">X86_CR4_OSFXSR</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU0ZYU1JfQklUXzA_"><span class="b">X86_CR4_OSFXSR_BIT</span></a><span class="f">)</span>
<a name="107" /><span class="Maybe">     107:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU1hNTUVYQ1BUX0JJVF8w"><span class="b">X86_CR4_OSXMMEXCPT_BIT</span></a>    <span class="c">10</span> <span class="k">/* enable unmasked SSE exceptions */</span>
<a name="108" /><span class="Maybe">     108:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU1hNTUVYQ1BUXzA_"><span class="b">X86_CR4_OSXMMEXCPT</span></a>    <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU1hNTUVYQ1BUX0JJVF8w"><span class="b">X86_CR4_OSXMMEXCPT_BIT</span></a><span class="f">)</span>
<a name="109" /><span class="Maybe">     109:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9WTVhFX0JJVF8w"><span class="b">X86_CR4_VMXE_BIT</span></a>    <span class="c">13</span> <span class="k">/* enable VMX virtualization */</span>
<a name="110" /><span class="Maybe">     110:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9WTVhFXzA_"><span class="b">X86_CR4_VMXE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9WTVhFX0JJVF8w"><span class="b">X86_CR4_VMXE_BIT</span></a><span class="f">)</span>
<a name="111" /><span class="Maybe">     111:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTVhFX0JJVF8w"><span class="b">X86_CR4_SMXE_BIT</span></a>    <span class="c">14</span> <span class="k">/* enable safer mode (TXT) */</span>
<a name="112" /><span class="Maybe">     112:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTVhFXzA_"><span class="b">X86_CR4_SMXE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTVhFX0JJVF8w"><span class="b">X86_CR4_SMXE_BIT</span></a><span class="f">)</span>
<a name="113" /><span class="Maybe">     113:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9GU0dTQkFTRV9CSVRfMA__"><span class="b">X86_CR4_FSGSBASE_BIT</span></a>    <span class="c">16</span> <span class="k">/* enable RDWRFSGS support */</span>
<a name="114" /><span class="Maybe">     114:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9GU0dTQkFTRV8w"><span class="b">X86_CR4_FSGSBASE</span></a>    <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9GU0dTQkFTRV9CSVRfMA__"><span class="b">X86_CR4_FSGSBASE_BIT</span></a><span class="f">)</span>
<a name="115" /><span class="Maybe">     115:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQ0lERV9CSVRfMA__"><span class="b">X86_CR4_PCIDE_BIT</span></a>    <span class="c">17</span> <span class="k">/* enable PCID support */</span>
<a name="116" /><span class="Maybe">     116:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQ0lERV8w"><span class="b">X86_CR4_PCIDE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9QQ0lERV9CSVRfMA__"><span class="b">X86_CR4_PCIDE_BIT</span></a><span class="f">)</span>
<a name="117" /><span class="Maybe">     117:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU1hTQVZFX0JJVF8w"><span class="b">X86_CR4_OSXSAVE_BIT</span></a>    <span class="c">18</span> <span class="k">/* enable xsave and xrestore */</span>
<a name="118" /><span class="Maybe">     118:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU1hTQVZFXzA_"><span class="b">X86_CR4_OSXSAVE</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9PU1hTQVZFX0JJVF8w"><span class="b">X86_CR4_OSXSAVE_BIT</span></a><span class="f">)</span>
<a name="119" /><span class="Maybe">     119:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTUVQX0JJVF8w"><span class="b">X86_CR4_SMEP_BIT</span></a>    <span class="c">20</span> <span class="k">/* enable SMEP support */</span>
<a name="120" /><span class="Maybe">     120:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTUVQXzA_"><span class="b">X86_CR4_SMEP</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTUVQX0JJVF8w"><span class="b">X86_CR4_SMEP_BIT</span></a><span class="f">)</span>
<a name="121" /><span class="Maybe">     121:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTUFQX0JJVF8w"><span class="b">X86_CR4_SMAP_BIT</span></a>    <span class="c">21</span> <span class="k">/* enable SMAP support */</span>
<a name="122" /><span class="Maybe">     122:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTUFQXzA_"><span class="b">X86_CR4_SMAP</span></a>        <a href="cpu.c_macros_ref.html#_X0JJVFVMXzA_"><span class="b">_BITUL</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0NSNF9TTUFQX0JJVF8w"><span class="b">X86_CR4_SMAP_BIT</span></a><span class="f">)</span>
<a name="123" /><span class="Maybe">     123:</span> 
<a name="124" /><span class="Maybe">     124:</span> <span class="k">/*</span>
<a name="125" /><span class="Maybe">     125:</span> <span class="k"> * x86-64 Task Priority Register, CR8</span>
<a name="126" /><span class="Maybe">     126:</span> <span class="k"> */</span>
<a name="127" /><span class="Maybe">     127:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0NSOF9UUFJfMA__"><span class="b">X86_CR8_TPR</span></a>        <a href="cpu.c_macros_ref.html#_X0FDXzA_"><span class="b">_AC</span></a><span class="f">(</span><span class="c">0x0000000f</span><span class="f">,</span><span class="b">UL</span><span class="f">)</span> <span class="k">/* task priority register */</span>
<a name="128" /><span class="Maybe">     128:</span> 
<a name="129" /><span class="Maybe">     129:</span> <span class="k">/*</span>
<a name="130" /><span class="Maybe">     130:</span> <span class="k"> * AMD and Transmeta use MSRs for configuration; see &lt;asm/msr-index.h&gt;</span>
<a name="131" /><span class="Maybe">     131:</span> <span class="k"> */</span>
<a name="132" /><span class="Maybe">     132:</span> 
<a name="133" /><span class="Maybe">     133:</span> <span class="k">/*</span>
<a name="134" /><span class="Maybe">     134:</span> <span class="k"> *      NSC/Cyrix CPU configuration register indexes</span>
<a name="135" /><span class="Maybe">     135:</span> <span class="k"> */</span>
<a name="136" /><span class="Maybe">     136:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9QQ1IwXzA_"><span class="b">CX86_PCR0</span></a>    <span class="c">0x20</span>
<a name="137" /><span class="Maybe">     137:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9HQ1JfMA__"><span class="b">CX86_GCR</span></a>    <span class="c">0xb8</span>
<a name="138" /><span class="Maybe">     138:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1IwXzA_"><span class="b">CX86_CCR0</span></a>    <span class="c">0xc0</span>
<a name="139" /><span class="Maybe">     139:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1IxXzA_"><span class="b">CX86_CCR1</span></a>    <span class="c">0xc1</span>
<a name="140" /><span class="Maybe">     140:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1IyXzA_"><span class="b">CX86_CCR2</span></a>    <span class="c">0xc2</span>
<a name="141" /><span class="Maybe">     141:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1IzXzA_"><span class="b">CX86_CCR3</span></a>    <span class="c">0xc3</span>
<a name="142" /><span class="Maybe">     142:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1I0XzA_"><span class="b">CX86_CCR4</span></a>    <span class="c">0xe8</span>
<a name="143" /><span class="Maybe">     143:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1I1XzA_"><span class="b">CX86_CCR5</span></a>    <span class="c">0xe9</span>
<a name="144" /><span class="Maybe">     144:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1I2XzA_"><span class="b">CX86_CCR6</span></a>    <span class="c">0xea</span>
<a name="145" /><span class="Maybe">     145:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9DQ1I3XzA_"><span class="b">CX86_CCR7</span></a>    <span class="c">0xeb</span>
<a name="146" /><span class="Maybe">     146:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9QQ1IxXzA_"><span class="b">CX86_PCR1</span></a>    <span class="c">0xf0</span>
<a name="147" /><span class="Maybe">     147:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9ESVIwXzA_"><span class="b">CX86_DIR0</span></a>    <span class="c">0xfe</span>
<a name="148" /><span class="Maybe">     148:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9ESVIxXzA_"><span class="b">CX86_DIR1</span></a>    <span class="c">0xff</span>
<a name="149" /><span class="Maybe">     149:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9BUlJfQkFTRV8w"><span class="b">CX86_ARR_BASE</span></a>    <span class="c">0xc4</span>
<a name="150" /><span class="Maybe">     150:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1g4Nl9SQ1JfQkFTRV8w"><span class="b">CX86_RCR_BASE</span></a>    <span class="c">0xdc</span>
<a name="151" /><span class="Maybe">     151:</span> 
<a name="152" /><span class="Maybe">     152:</span> 
<a name="153" /><span class="True">     153:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */</span>
<a name="154" /><span class="True">     154:</span> </pre>
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